The invention is generally related to the field of forming semiconductor devices and more specifically to hardmasks for dielectric etches, such as those used in forming copper interconnects.
As semiconductor devices become more and more dense, it becomes more and more difficult to pattern the increasingly smaller geometries. This is especially true when forming dual damascene copper interconnects. In dual damascene copper interconnects, the dielectric is formed first. Interconnects are formed by etching the dielectric and then filling with appropriate barrier materials and copper. A trench is etched in an upper dielectric and a via is etched through a lower dielectric. The filled trench forms the interconnect lines/structures and filled vias provide connection to lower interconnect layers.
Vias and trenches typically have high aspect ratios. It can be difficult to etch high aspect ratio structures. One problem that occurs is that the pattern used for an etch tends to erode during the etch. An eroding pattern causes unacceptably high critical dimension (CD) variation.
The invention uses an aluminum hardmask for etching a dielectric layer. The aluminum hardmask is able to withstand the dielectric etch without etching.
An advantage of the invention is providing a method for patterning a dielectric layer with improved CD control.
This and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.